1. Technical Field
This invention relates to data synchronizers and, more particularly, to data synchronizers for synchronizing data to a faster clock rate.
2. Discussion
As the use of microprocessor-based control systems increases, the need for data synchronization increases. Often external data sources connected to the microprocessor system generate data at an external clock rate which is slower than an internal clock rate of the microprocessor. The data sources can be multi-bit, for example 16- and 32-bit, gate arrays. In one application, the data synchronizer synchronizes radar sensor data to an internal clock rate of an aircraft's microprocessor.
Conventional data synchronizers typically use first-in-first-out (FIFO) or ping-pong memories. These conventional data synchronizers operate effectively, however, they use a significant number of gates. For example, synchronizing a 32-bit data path using a 32.times.16 bit FIFO memory requires at least 12,000 gates in addition to control logic.
Therefore it is desirable to design an asynchronous data synchronizer using fewer gates to decrease size, cost, and complexity.